现代雷达2025，Vol.47Issue(6)：30-38,9.DOI:10.16592/j.cnki.1004-7859.20240229001
基于FPGA的SAR图像目标检测加速器设计
Design of SAR Image Target Detection Accelerator Based on FPGA
摘要
Abstract
The mainstream synthetic aperture radar(SAR)image target detection algorithms based on central processing unit(CPU)and graphics processing unit(GPU)have disadvantages such as large model size,high computational complexity,low par-allelism,and high power consumption,and are not suitable for deployment on resource limited platforms such as satellites and un-manned aerial vehicles.A SAR image target detection accelerator based on field programmable gate array(FPGA)is designed in this paper,taking into account the board resources,power consumption,inference speed and accuracy.The network model adopt-ed by the accelerator is an optimized YOLOv4-tiny architecture,which optimizes the data bit width with a 16-bit fixed-point quanti-zation and adds dilated convolutions to replace standard convolutions,thereby reducing the network model and parameters for de-ployment on resource limited FPGA.In the implementation of FPGA convolutional layers,multiple loops unrolling and loop blocks parallelism methods are used to accelerate convolution operations.The experimental results show that the optimized algorithm achieved a throughput of 15.24 GOPS on FPGA,with a recognition speed of 256 ms per image,which is between CPU and GPU.However,due to the FPGA hardware power consumption of only 3.06 W,the energy efficiency ratios of the proposed algorithm reach 18.4 times and 7.3 times that of CPU and GPU respectively.关键词
现场可编程门阵列/合成孔径雷达/硬件加速器/YOLOv4-tiny网络/目标检测Key words
field programmable gate array(FPGA)/synthetic aperture radar(SAR)/hardware accelerator/YOLOv4-tiny net-work/object detection分类
电子信息工程引用本文复制引用
汤亮,王小华,陈立福..基于FPGA的SAR图像目标检测加速器设计[J].现代雷达,2025,47(6):30-38,9.基金项目
国家自然科学基金资助项目(41201468) （41201468）
