电子器件2025，Vol.48Issue(3)：481-487,7.DOI:10.3969/j.issn.1005-9490.2025.03.002
应用于时间数字转换器的小数分频PLL设计
Design of a Fractional PLL for Time to Digital Converter
摘要
Abstract
High precision TDC is widely used in all digital phase-locked loops for quantifying the fractional phase difference between in-put reference signals and feedback signals.In order to reduce the sensitivity of the delay unit in TDC to changes in process corners,power supply voltage and temperature conditions,the control voltage of analog PLL VCO is usually used to control the change of delay.The TSMC 28 nm process is adopted to design a decimal PLL for high-precision time to digital converters.Unlike traditional architec-tures,the use of gated charge pump and sampling loop filter structures significantly reduces the ripple amplitude of the voltage controlled voltage(Vctrl).The simulation results show that under the conditions of 2.5 V power supply voltage and 96 MHz reference clock input,the PLL output frequency range is 2 160 MHz-3 481 MHz,and the RMS jitter of the PLL is 254 fs at the output frequency of 3.481 GHz,which can meet the application requirements of high-precision TDC systems.关键词
高精度/门控电荷泵/采样环路滤波器/控制电压/抖动Key words
high precision/gated charge pump/sampling loop filter/control voltage/jitter分类
信息技术与安全科学引用本文复制引用
欧熙,吴金..应用于时间数字转换器的小数分频PLL设计[J].电子器件,2025,48(3):481-487,7.基金项目
江苏省研究生科研与实践创新计划项目(SJCX21_0038) （SJCX21_0038）
国家自然科学基金(62174028) （62174028）
