电子器件2025，Vol.48Issue(3)：488-494,7.DOI:10.3969/j.issn.1005-9490.2025.03.003
一种基于FPGA的高分辨率和线性度的全数字DCDL
An All-Digital DCDL with High Resolution and Linearity Based on FPGA
摘要
Abstract
A design of an all-digital digitally-controlled delay line(ADCDL)with high resolution and high linearity is proposed.The de-signed ADCDL is based on the digital elements available in common FPGA and it consists of a multi-input chain of delay elements,a high fan-out distribution network(HFDN)and a control encoder.The multi-input chain of delay elements acts as a distributed multi-plexer and an HFDN with minimum skew is used to drive the multi-input chain of delay elements.The proposed design can be integrat-ed in a completely digital design process.Synthesized and simulated with hardware description languages,it relies only on tools for auto-mated placement and routing of digital circuits.Finally,an ADCDL prototype is implemented based on Xilinx Kintex-7 FPGA.The ex-perimental results show that the proposed design scheme not only has high resolution and high linearity in terms of delay performance,but also has portability,and can be extended without additional workload.关键词
数据采集/计时分配/数字控制延迟线/延迟元件链/现场可程式门阵列/算术进位原语/分辨率Key words
data acquisition/timing allocation/digitally-controlled delay line/delay element chain/field programmable gate array/arith-metic carry primitive/resolution分类
信息技术与安全科学引用本文复制引用
韦家正,覃晓..一种基于FPGA的高分辨率和线性度的全数字DCDL[J].电子器件,2025,48(3):488-494,7.基金项目
2022年度广西高校中青年教师科研基础能力提升项目(2022KY1129,2022KY1130) （2022KY1129,2022KY1130）
