集成电路与嵌入式系统2025，Vol.25Issue(7)：15-21,7.DOI:10.20193/j.ices2097-4191.2025.0019
应用于TDC的多级高精度DLL的设计
Design of multi-level high-precision DLL applied to TDC
摘要
Abstract
High-precision TDC requires a multiphase clock with low jitter and low latency to ensure its normal operation.Therefore,a variety of key technologies have been adopted to optimize the design of core modules such as the structure of the DLL system,charge pump,voltage-controlled delay line,and lock detection circuit.Sub-gate-level delay line technology enables DLL systems to generate multi-phase clock signals with a delay of only 1.25 ps.The design of the three-level structure enables the DLL system to get rid of the reliance on high-precision and high-frequency reference clock signals,and it can work normally using a 100 MHz reference clock signal.The application of technologies such as current steering and dual clamping can effectively suppress the influence of non-ideal effects such as charge sharing and channel length modulation,and effectively improve the performance of static phase error and peak-to-peak jitter.Based on the 65 nm process of TSMC,this paper has completed the design,simulation and wafer fabrication verification of the circuit.The simulation results show that the DLL system can achieve the set functions.The post-simulation results are as follows:The static phase error is approximately 13.1 ps,the peak-to-peak jitter performance is approximately 1.01 ps,and the system power consumption is 82.5 mW.Ultimately,the test results show that the frequency range of the system is approximately 50～320 MHz,and the locking time is approximately 117.5 μs.关键词
延迟锁相环/压控延迟线/电荷泵/TDCKey words
delay-locked loop/voltage controlled delay line/charge pump/TDC分类
信息技术与安全科学引用本文复制引用
许嘉珩,卢宏斌,汪家奇,常玉春,申人升..应用于TDC的多级高精度DLL的设计[J].集成电路与嵌入式系统,2025,25(7):15-21,7.基金项目
国家重点研发计划课题(2023YFB4503003) （2023YFB4503003）
辽宁省科技计划联合计划项目(2024JH2/102600042) （2024JH2/102600042）
