摘要
Abstract
PowerPC460 is a 32-bit embedded processor that supports hard floating-point mode.It features a set of 32-bit general-purpose registers and 64-bit floating-point registers.The GCC compiler generates a supporting toolchain for this professor.By default,when handling data operations,the GCC toolchain leverages the floating-point registers to access 64-bit integer data.This approach effectively reduces the number of operation instructions and the overall register usage,enhancing computational efficiency.However,challenges a-rise from the disparity in data alignment between floating-point and general-purpose registers.When floating-point registers are utilized for integer data processing,the accessed memory address must strictly comply with the bit-width requirements of the data type.Failure to meet this alignment criterion can lead to runtime alignment exceptions.Moreover,when the operating system performs context switching for integer operation tasks,it requires additional protection support for the data in floating-point registers.This requirement incurs additional overhead,degrading system performance.To address these issues,this article presents an optimized strategy for the instruction generation module of the GCC compiler.The proposed method advocates using general-purpose registers to execute 64-bit in-teger data operations in the hard floating-point mode.Additionally,a new compilation option is introduced,retaining the original global optimization scheme.A domestically produced embedded operating system is experimentally deployed at the PowerPC460 board level for functional and performance testing.The results indicate that,while maintaining correct functional behavior,the optimized approach a-chieves approximately a 6.3％improvement in task switching time,demonstrating its practical value in enhancing system performance.关键词
PowerPC460/对齐异常/编译器优化/嵌入式操作系统Key words
PowerPC460/alignment exception/compiler optimization/embedded operating system分类
信息技术与安全科学
