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ParaGraph:a parallel graph computing accelerator based on software-hardware collaboration

邓军勇

高技术通讯（英文版）2025，Vol.31Issue(2)：105-117,13.

高技术通讯（英文版）2025，Vol.31Issue(2)：105-117,13.DOI:10.3772/j.issn.1006-6748.2025.02.001

ParaGraph:a parallel graph computing accelerator based on software-hardware collaboration

邓军勇¹

作者信息

折叠

摘要

关键词

graph computing/software-hardware co-design/reduced instruction set compu-ting-five(RISC-V)/parallel accelerator

Key words

graph computing/software-hardware co-design/reduced instruction set compu-ting-five(RISC-V)/parallel accelerator

引用本文复制引用

邓军勇..ParaGraph:a parallel graph computing accelerator based on software-hardware collaboration[J].高技术通讯（英文版）,2025,31(2):105-117,13.

基金项目

Supported by the National Key R&D Program of China(No.2022ZD0119001),the National Natural Science Foundation of China(No.61834005),the Shaanxi Province Key R&D Plan(No.2022GY-027,2021GY-029)and the Key Scientific Research Project of Shaanxi Depart-ment of Education(No.22JY060). （No.2022ZD0119001）

高技术通讯（英文版）

ISSN：1006-6748

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