电子科技大学学报2025，Vol.54Issue(4)：488-493,6.DOI:10.12178/1001-0548.2024148
集成双输入缓冲前端的4GS/s 13位TI-Pipelined-SAR ADC
A 4GS/s 13-bit TI-Pipelined-SAR ADC with integrated dual-input buffer
摘要
Abstract
As the conversion rate increases,the sampling front-end gradually becomes a bottleneck limiting the performance of high-speed and high-resolution analog-to-digital converters(ADCs).A 4GS/s 13-bit time-interleaved-pipelined-successive approximation register(TI-Pipelined-SAR)ADC with an integrated dual-input buffer is implemented in a 16 nm FinFET process.To minimize the intra-channel kickbacks and the crosstalk between multi-channel sampling switches,a dual-input buffer structure is adopted.Additional offset mismatch and gain mismatch introduced by dual-input buffer are corrected using an inter-channel calibration algorithm.An all-CMOS fast turn-on bootstrapped sampling switch circuit is also presented to improve the sampling rate.With 500 MHz input,the ADC achieves a spurious free dynamic range(SFDR)of 74.1 dBc and a signal-to-noise distortion ratio(SNDR)of 59.6 dB.关键词
模数转换器/输入缓冲前端/校准算法/栅压自举采样电路Key words
analog-to-digital converter(ADC)/input buffer/calibration algorithm/bootstrapped sampling switch circuit分类
信息技术与安全科学引用本文复制引用
陈浩然,俞军..集成双输入缓冲前端的4GS/s 13位TI-Pipelined-SAR ADC[J].电子科技大学学报,2025,54(4):488-493,6.
