通信与信息技术Issue(4)：18-21,35,5.
一种基于FPGA与JESD204B实现多级协同时间交织采集的方法
A method of multi-stage collaborative TIADC based on FPGA and JESD204B
李康 1项世珍1
作者信息
- 1. 中国电子科技集团公司第五十二研究所,浙江 杭州 311100
- 折叠
摘要
Abstract
As one single Analog-to-Digital Converter(ADC)is gradually difficult to meet the requirements of large bandwidth and high sampling rate,one effective solution is Time-Interleaved ADC(TIADC).Taking advantage of the strong computing power of Field Programmable Gate Array(FPGA)and the strict timing of JESD204B,and combining the high performance of the TIADC inside the chip and the flexibility and efficiency of the TIADC outside the chip,a multi-stage collaborative TIADC method for intra-chip and inter-chip is proposed,which is suitable for sampling high-frequency broadband signals.In addition,key technologies such as clock circuit design and inter-channel difference estimation are discussed.The experimental results show that the two ADCs,each with 4 active cores,achieve a sampling rate of 10Gsps through three-stage TIADC,and the Spurious Free Dynamic Range(SFDR)is greater than 48dB,which can greatly meet the requirements of high-frequency and broadband signal sampling for radar detection,mobile communication and measuring instruments.关键词
模数转换器/时间交织模数转换/现场可编程门阵列/JESD204B/无杂散动态范围Key words
Analog-to-Digital Converter(ADC)/Time-interleaved ADC(TIADC)/Field Programmable Gate Array(FPGA)/JESD204B/Spurious Free Dynamic Range(SFDR)分类
信息技术与安全科学引用本文复制引用
李康,项世珍..一种基于FPGA与JESD204B实现多级协同时间交织采集的方法[J].通信与信息技术,2025,(4):18-21,35,5.
