集成电路与嵌入式系统2025，Vol.25Issue(8)：74-80,7.DOI:10.20193/j.ices2097-4191.2025.0051
基于Cortex-M3内核的PCIe RP系统设计与实现
Design and implementation of PCIe RP system based on Cortex-M3 kernel
摘要
Abstract
PCIe and SRIO are the mainstream high-speed communication interface protocols.In the large data application scenario repre-sented by artificial intelligence,achieving the compatibility of the above protocols is the key to build a large computing power system to break through the bottleneck of storage and computing power.In view of the above requirements,CIP interconnection core realizes multi-protocol conversion interaction such as PCIe,SRIO,DDR and NAND FLASH with a unified routing network.Among them,PCIe is the main human-computer interaction interface,and the construction of PCIe RP system is the basis of PCIe communication.The existing PCIe reading and writing devices based on operating system have some problems,such as high delay and poor operability.In order to solve the above problems,a PCIe RP system is built based on Cortex-M3 processor,and the corresponding drivers and soft-ware are developed,which realizes efficient and accurate data transmission between PCIe and various devices.On the basis of realizing the basic functions,the stability tests of 50 000 times,100 000 times and 150 000 times of large-scale data interaction were completed respectively.The results show that the system has good stability in large-scale data interaction events.It provides a solution for data in-teraction between processor and PCIe.关键词
PCIe/SRIO/DDR/NAND FLASH/互联标准/数据交互/Cortex-M3/驱动开发Key words
PCIe/SRIO/DDR/NADN FLASH/interconnection standard/data interaction/Cortex-M3/drive development分类
信息技术与安全科学引用本文复制引用
徐俊杰,魏敬和,刘国柱,何健,张正..基于Cortex-M3内核的PCIe RP系统设计与实现[J].集成电路与嵌入式系统,2025,25(8):74-80,7.基金项目
江苏省自然科学基金(BK20232029) （BK20232029）
江苏省揭榜挂帅项目(BE2023005) （BE2023005）
