现代电子技术2025，Vol.48Issue(19)：77-83,7.DOI:10.16652/j.issn.1004-373x.2025.19.013
低FPGA硬件资源消耗的SC-FDE定时同步方案研究
Research on SC-FDE timing synchronization scheme with low FPGA hardware resource consumption
胡海勤 1韩文璇 1张锐1
作者信息
- 1. 中国电子科技集团公司第五十研究所,上海 200331
- 折叠
摘要
Abstract
As modern SC-FDE(single-carrier frequency-domain equalization)communication systems are becoming increasingly complex,the contradiction between the implementation schemes of communication systems and the limited FPGA hardware resources has become more and more acute.In view of this,a de-normalized short sequence SC-FDE timing synchronization algorithm is proposed.The algorithm requires that the content of timing synchronization sequence of SC-FDE signal shall be transformed into three consecutive identical m-sequences,and the total length of the sequence remains unchanged.In comparison with the traditional cross-correlation algorithm,the proposed algorithm has a performance loss of 0.5 dB in AWGN channel with low SNR,but the FPGA implementation scheme based on this algorithm can save up to 70.2%look-up tables,60.4%registers and all digital signal processing units in comparison with the FPGA implementation scheme based on the traditional cross-correlation SC-FDE timing synchronization algorithm.The proposed algorithm and implementation scheme can alleviate the dilemma of insufficient FPGA hardware resources and high hardware cost faced by SC-FDE communication systems.关键词
单载波频域均衡/定时同步算法/资源节省/FPGA/互相关/定时度量函数Key words
SC-FDE/timing synchronization algorithm/resource saving/FPGA/cross-correlation/timing evaluation function分类
信息技术与安全科学引用本文复制引用
胡海勤,韩文璇,张锐..低FPGA硬件资源消耗的SC-FDE定时同步方案研究[J].现代电子技术,2025,48(19):77-83,7.
