集成电路与嵌入式系统2025，Vol.25Issue(9)：45-56,12.DOI:10.20193/j.ices2097-4191.2025.0035
轻量化超分辨率算法的FPGA硬件实现与适配优化
FPGA-based hardware implementation and adaptation optimization of a lightweight super-resolution algorithm
摘要
Abstract
To Address the resource constraints and energy efficiency bottlenecks in FPGA deployment of super-resolution networks,a lightweight hardware acceleration solution for the ESPCN super-resolution network is proposed.At the algorithm level,the ESPCN net-work is simplified to significantly reduce its computational complexity,and 16-bit fixed-point quantization is employed to further enhance computing efficiency.In the hardware architecture design,targeted optimizations are implemented for the hard-ware realization of standard convolution,pointwise convolution,and sub-pixel convolution.The experimental results indicate that the accelerator deployed on the ZYNQ7035 platform,operating at 210 MHz,efficiently reconstructs a 480×270 resolution image to 1 920× 1 080 resolution,with a forward inference time of only 49.8 ms per image and a total on-chip power consumption of 4.17 W.关键词
超分辨率网络/硬件加速器/FPGA/ZYNQ异构平台Key words
super-resolution network/hardware accelerator/FPGA/ZYNQ heterogeneous platform分类
信息技术与安全科学引用本文复制引用
王毅,张平娟,郭世俊..轻量化超分辨率算法的FPGA硬件实现与适配优化[J].集成电路与嵌入式系统,2025,25(9):45-56,12.基金项目
国家级大学生创新训练项目(202410879012) （202410879012）
