单片机与嵌入式系统应用2025，Vol.25Issue(10)：47-54,8.DOI:10.20193/j.ices2097-4191.2025.0010
112 Gb/s SerDes电路关键技术综述
Review for 112 Gb/s SerDes circuit key technology
摘要
Abstract
High-speed SerDes rates have progressed from 56 Gb/s to 112 Gb/s and beyond.Maintaining signal integrity at such ultra-high speeds while balancing power consumption,reliability,flexibility,and cost-effectiveness is a hot topic in current research.This pa-per reviews key technologies for 112 Gb/s SerDes from four perspectives:transmitter,receiver,clock structure,and low-power tech-niques,based on the current mainstream architecture of analog-to-digital conversion and digital signal processing.This exploration is provided as a reference for research related to high-speed SerDes technology.关键词
112 Gb/s SerDes/发送器/接收器/均衡Key words
112 Gb/s SerDes/transmitter/receiver/equalization分类
信息技术与安全科学引用本文复制引用
董春雷,赵博,吕平,李沛杰,张霞..112 Gb/s SerDes电路关键技术综述[J].单片机与嵌入式系统应用,2025,25(10):47-54,8.基金项目
国家重点研发计划微纳电子技术专项(2023YFB4404201) （2023YFB4404201）
