单片机与嵌入式系统应用2025，Vol.25Issue(10)：75-81,7.DOI:10.20193/j.ices2097-4191.2025.0034
一种空间阵列式处理器内核设计
Design of spatial array-based processor core
刘玉 1张杰 1刘谷1
作者信息
- 1. 安徽芯纪元科技有限公司,合肥 230088
- 折叠
摘要
Abstract
This paper proposes a spatial array-based processor core design,eliminating the need for centralized register files.Through the design,computing units communicate data via an interconnect bus and perform computations directly through local memory.The pro-cessing results from local computing units are propagated to other units via a broadcast bus.This organization exhibits linear scalability,as the scale of computing units is not constrained by centralized components.It further incorporates flexible broadcast and reduction mechanisms that better align with algorithmic data communication patterns,facilitating efficient algorithm mapping and physical imple-mentation.The processing element array implemented based on this design has high performance scalability,with a unit area perform-ance of up to 1.4 TOPS/mm2@INT8,the performance to power ratio reaches 2.47 TOPS/W.This makes it well-suited for large-scale deployment as a high computing power processor processing core.关键词
处理器/内核/阵列/扩展性/数字信号Key words
processor/core/array/scalability/digital signal分类
信息技术与安全科学引用本文复制引用
刘玉,张杰,刘谷..一种空间阵列式处理器内核设计[J].单片机与嵌入式系统应用,2025,25(10):75-81,7.
