空天预警研究学报2025，Vol.39Issue(5)：360-364,5.DOI:10.3969/j.issn.2097-180X.2025.05.010
一种基于FPGA的高并行度LDPC编译码设计
A high-parallelism LDPC encoding and decoding design based on FPGA
摘要
Abstract
In order to leverage LDPC encoding and decoding technology in radar communication and satellite communication,making full use of the advantages that the field programmable gate array(FPGA)contains a large amount of programmable logic resources and storage resources,this paper accords to the structural characteristics of quasi-cyclic LDPC codes to design a FPGA-based high-parallel LDPC codec.The coding and decoding algo-rithm can be compatible to other types of quasi-cyclic LDPC codes by reading in different LDPC check matrices,and also has high universality and scalability.The implementation of this codec on the XC7VX690T indicates that the usage rate of logic units(LUTs)does not exceed 35%,that of bipolar random access memory(BRAM)not ex-ceed 23%,and that the occupied logic resources and storage resources in time of decoding can be reduced through puncturing and shortening of LDPC codes.关键词
LDPC码/第5代移动通信新无线标准/译码器/编码器/现场可编辑逻辑阵列Key words
LDPC code/5G NR/decoder/encoder/FPGA分类
信息技术与安全科学引用本文复制引用
艾雷..一种基于FPGA的高并行度LDPC编译码设计[J].空天预警研究学报,2025,39(5):360-364,5.
