计算机技术与发展2025，Vol.35Issue(10)：10-17,8.DOI:10.20165/j.cnki.ISSN1673-629X.2025.0146
基于ZYNQ的神经网络硬件加速器设计
Neural Network Hardware Accelerator Design Based on ZYNQ
摘要
Abstract
To solve the problem of high power consumption of traditional neural network accelerators,a hardware accelerator based on ZYNQ chip is proposed.According to the characteristics of the deployed YOLOv3-tiny algorithm,the accelerator uses a hardware and software collaboration method to split the algorithm on the ZYNQ heterogeneous platform.The PS side of ZYNQ is responsible for tasks suitable for serial CPU scheduling,and the PL side is responsible for complex parallel computing,taking full advantage of each other.At the same time,the use of multiplier and adder is optimized,two 8-bit multiplication operations are realized with one DSP,and the adder structure of trinomial tree is used instead of binary tree,so that the resource consumption and timing of the system are further optimized.After completing the design of each circuit module,the system was concatenated,and the system was tested on ZYNQ platform.The ex-perimental results showed that the system only used 18.15%BRAM resources and 14.65%DSP resources,the power consumption was only 2.144 W,and the energy efficiency ratio reached 12.66,which was significantly improved compared with the GPU and CPU platforms.It is proved that the system can achieve high performance target detection under low power consumption and is very suitable for deployment to embedded mobile terminal.关键词
ZYNQ/神经网络/硬件加速器/ARM/现场可编程门阵列Key words
ZYNQ/neural network/hardware accelerator/ARM/field-programmable gate array(FPGA)分类
信息技术与安全科学引用本文复制引用
刘子浩,赖嘉伟,查宇恒,唐珂,徐荣青,孙科学..基于ZYNQ的神经网络硬件加速器设计[J].计算机技术与发展,2025,35(10):10-17,8.基金项目
江苏省研究生实践创新计划(SJCX24_0309) （SJCX24_0309）
