摘要
Abstract
In the contemporary landscape,the performance demands placed on microprocessors are continually escalating.Consequently,efficiently reducing delays on critical paths has become a crucial research challenge.To address this significant problem,we propose a timing optimization method based on logic local remapping specifically targeting critical paths.This method integrates critical path infor-mation to construct localized,small netlist subsets within the topological network surrounding the critical paths.Subsequently,each of these localized small netlists undergoes a remapping process.During this process,a netlist pool is established to store multiple sets of results generated after synthesis with varying parameters.Finally,the remapped small netlist exhibiting the best timing characteristics is selected from this pool to replace the original local netlist segment.We have implemented the aforementioned algorithm and conducted experiments on seven open-source designs.The experiments were performed using the Nangate 45 typical process corner and the Open-ROAD physical design tool flow.The results demonstrate that,across these seven open-source designs,the optimized netlists achieved through our method exhibit significant improvements in timing slack.Specifically,the Worst Negative Slack(WNS)shows an improve-ment of at least 1.120％,and the Total Negative Slack(TNS)shows an improvement of at least 11.646％.These substantial gains val-idate the effectiveness of the proposed method in meeting the stringent timing constraints inherent in high-performance microprocessor design.This approach provides a potent solution for enhancing timing closure in advanced digital circuits.关键词
物理设计/逻辑综合/关键路径/时序优化/重映射Key words
physical design/logical synthesis/critical path/timing optimization/remapping分类
电子信息工程
