集成电路与嵌入式系统2025，Vol.25Issue(11)：8-14,7.DOI:10.20193/j.ices2097-4191.2025.0070
基于22 nm FD-SOI工艺的宽电压高能效运算电路设计
Design of energy-efficient op-circuit with wide-voltage based on 22 nm FD-SOI process
摘要
Abstract
This paper presents the design and implementation of a high-efficiency computing circuit chip based on the 22 nm FD-SOI process,covering a wide voltage range from 0.2 V to 0.8 V.The paper conducts a comparative analysis and optimization of energy effi-ciency across four levels:architectural design,cell library selection,low-power logic synthesis,and physical design.By implementing and simulating different computing architectures,the paper identifies the optimal architectural design with the best overall performance.Standard cell libraries with different channel lengths and threshold voltages are evaluated,and a mix of high-drive and low-leakage cells are used to balance performance and power consumption.The optimized energy efficiency is reduced to 102.64 fJ/Op,representing a 17.5％improvement over a single-type cell design.During the logic synthesis stage,the DesignWare-LP flow is applied,achieving a 6.7％improvement in energy efficiency through logic reorganization and low-power cell replacement.During the physical design phase,unit density is controlled to further reduce parasitic capacitance.We validated the optimized chip through tape-out verification,with test results showing:at a 0.24 V operating voltage,the energy efficiency of the adder and multiplier reached 1.55 fJ/Op and 14.1 fJ/Op,respectively,with latency below 100 ns,effectively addressing the shortcomings of existing solutions in terms of wide voltage adaptability or multi-dimensional energy efficiency optimization.关键词
绝缘体上硅/FD-SOI/架构对比/单元库选择Key words
silicon on insulator/FD-SOI/architecture comparison/cell library selection分类
信息技术与安全科学引用本文复制引用
杨雅楠,裴秉玺,张光达,赵夏,钟智勇,何卫锋..基于22 nm FD-SOI工艺的宽电压高能效运算电路设计[J].集成电路与嵌入式系统,2025,25(11):8-14,7.基金项目
北京市科技新星计划资助 （）
