集成电路与嵌入式系统2025，Vol.25Issue(11)：71-81,11.DOI:10.20193/j.ices2097-4191.2025.0071
AXI协议跨芯粒传输的架构设计与实现
Design and implementation of a cross-die transmission architecture for AXI protocol
摘要
Abstract
With the ever-increasing demand for computational power and chip performance,multi-chiplet integration has emerged as a critical approach to enhancing integration density and processing capabilities.The chiplet interconnect interface serves as the key enabler for chiplet architectures,where compatibility design-particularly supporting diverse interconnect protocols-poses significant challenges.Given the widespread adoption of the AXI protocol in System-on-Chip(SoC)designs,achieving efficient AXI compatibility in chiplet in-terconnects is of substantial importance.This paper presents a comprehensive cross-die AXI transmission architecture circuit designed at the protocol layer based on an in-house chiplet interconnect standard,implementing a local agent-based flow control mechanism to man-age AXI channel handshaking across dies.We detail the methodology for mapping AXI protocol signals to interconnect data packets to enable end-to-end transmission.The functional correctness is verified through a Universal Verification Methodology(UVM)testbench,with performance evaluated via an FPGA validation platform.Under 1 024-bit read/write data widths during 4KB burst write opera-tions,the measurement showed 85-clock-cycle transmission latency(theoretical minimum:64 cycles)and 84.92％bandwidth utilization at 1 GHz interconnect frequency.This work provides a systematic reference for protocol layer design in chiplet interconnect standards to adapt AXI or similar communication protocols.关键词
芯粒/互联接口/AXI协议/跨芯粒传输架构/FPGA测试方法Key words
chiplet/interconnect interface/AXI protocol/cross-die transmission architecture/FPGA testing methodologies分类
计算机与自动化引用本文复制引用
宋朝阳,周宏伟,马驰远,刘宇骢,梁杰,李焓响,周雨萱,陈志强..AXI协议跨芯粒传输的架构设计与实现[J].集成电路与嵌入式系统,2025,25(11):71-81,11.基金项目
高性能计算国家重点实验室自主课题—面向大模型的人工智能加速器三维堆叠存储系统(202401-04) （202401-04）
