电工技术学报2025，Vol.40Issue(22)：7250-7262,13.DOI:10.19595/j.cnki.1000-6753.tces.242198
亚阈值摆幅法解析表征SiC MOSFET陷阱电荷及其BTI机理分析应用
Analytical Characterization of Trapped Charge in SiC MOSFETs Using Subthreshold Swing Method and Its Application in Bias Temperature Instability Mechanism Analysis
摘要
Abstract
Owing to superior performance metrics in blocking voltage,operating temperature,switching speed,and switching loss,SiC MOSFETs are gradually replacing traditional silicon-based devices in fields such as photovoltaics and electric vehicles.Nevertheless,the widespread adoption of SiC MOSFETs is hindered by critical reliability challenges,particularly their exceptionally high interface state density(DIT),which induces threshold voltage drift under bias temperature instability(BTI)and severely compromises gate oxide reliability.Therefore,it is necessary to characterize the interface state density to analyze the degradation mechanism of devices under BTI. Conventional DIT characterization methods predominantly rely on capacitance-voltage(C-V)measurements,which unavoidably face the challenge of decoupling the interface trap capacitance(CIT)from the total measured capacitance.Alternatively,some methods require specialized equipment,often involving complex protocols and time-consuming measurement cycles.In contrast,the method based on analyzing the slope change of the I-V characteristic in the subthreshold region is simple,rapid,and convenient,making it particularly suitable for characterizing degraded devices.In this work,the classical I-V method is further developed into an analytical expression of the subthreshold swing(SS)to DIT using the concept of infinitesimal analysis.On one hand,it circumvents the difficulty of precisely separating CIT,enabling measurements on conventional MOSFET devices without the need for special test structures.On the other hand,the proposed formula links DIT to SS,revealing an explicit linear proportionality between the two.Consequently,researchers can infer the distribution of DIT across the energy band by observing how the SS varies with energy level,which is crucial for understanding the impact of interface states and improving device performance. Furthermore,to minimize the influence of factors other than initial voltage stress amplitude,stress time,and temperature,the paper discusses the roles of scan direction,scan speed,scan delay time,measurement time,and charge-clearing pretreatment.The results indicate that:(1)the device must be shorted to ground before every change of measurement condition to erase residual stress history;(2)I-V characteristics should be recorded with a descending step-voltage waveform rather than an ascending scan to prevent underestimation of trapped charge arising from surface-polarity reversal;and(3)reducing both scan delay and measurement time increases the effective scan rate,thus maximizing the retention of the effect of initial electrothermal stress on trapped charge. Finally,the effects of different electrothermal stress conditions,including initial voltage stress amplitude,stress time,and temperature,are quantified.The results show that the variation of trapped charge correlates strongly with the magnitude of threshold voltage drift,demonstrating that trapped charge variation is the principal driver of this drift.Due to the charge-memory characteristic of traps,distinct electrothermal stress histories result in different amounts of charge captured in device traps,leading to non-uniform threshold voltage drift.The intrinsically high DIT of SiC MOSFETs produces a large SS at low temperature,which deteriorates further with increasing electrothermal stress.Under favorable electrothermal stress conditions,the initial voltage-stress amplitude scales approximately linearly with both trapped charge and threshold-voltage drift.In contrast,the initial voltage-stress time exhibits an exponential dependence on both of these quantities. These findings provide rapid assessment guidance of DIT and offer efficient tools for accelerating the process production testing flow and enhancing the gate oxide reliability of SiC MOSFETs.关键词
SiC MOSFET/界面态密度/亚阈值摆幅/陷阱电荷/阈值电压/漂移Key words
SiC MOSFET/interface state density/subthreshold swing/trapped charge/threshold voltage/drift分类
电子信息工程引用本文复制引用
施超,李学宝,王来利,王跃,蒋馨玉,陈中圆,冉立..亚阈值摆幅法解析表征SiC MOSFET陷阱电荷及其BTI机理分析应用[J].电工技术学报,2025,40(22):7250-7262,13.基金项目
北京怀柔实验室资助项目(ZD2022004A). （ZD2022004A）
