集成电路与嵌入式系统2025，Vol.25Issue(12)：1-7,7.DOI:10.20193/j.ices2097-4191.2025.0063
异构神经网络芯片片上网络的行为级仿真器设计
Behavioral-level simulator design for network-on-chip in heterogeneous neural network chips
摘要
Abstract
As neural network models become increasingly complex,Network-on-Chip(NoC)plays a critical communication role in heter-ogeneous computing systems.However,the traditional NoC simulation tools generally lack support for heterogeneous computing units such as matrix processing units and RISC-V programmable cores,making it difficult to meet the requirements of large-scale AI tasks in terms of real-time performance,throughput,and energy efficiency.To address these challenges,this paper proposes and implements a behavior-level NoC simulation framework for heterogeneous computing.The framework features high-precision node modeling,a dy-namic pipelining mechanism,a hybrid task-aware routing algorithm,and full-path visualization and debugging capabilities.The experi-mental results demonstrate that the proposed framework significantly outperforms traditional methods in average latency,throughput,and visualization debugging efficiency.Notably,it exhibits greater stability and scalability in scenarios involving hybrid task flows and hardware faults,providing strong support for the design and optimization of NoC in next-generation intelligent computing platforms.关键词
异构计算/片上网络/行为级仿真/动态流水线/混合路由算法/AI加速器Key words
heterogeneous computing/network-on-chip/behavior-level simulation/dynamic pipeline/hybrid routing algorithm/AI hardware分类
信息技术与安全科学引用本文复制引用
WU Liangshun,TAO Tao,ZHANG Bin..异构神经网络芯片片上网络的行为级仿真器设计[J].集成电路与嵌入式系统,2025,25(12):1-7,7.基金项目
新疆政法学院校长基金(XZZK2022002) （XZZK2022002）
上海交通大学科研预研基金项目 （）
教育部嵌入式系统与服务计算重点实验室开放课题(ESS-CKF2024-10) （ESS-CKF2024-10）
上海市高可信计算重点实验室开放课题(24Z670103399) （24Z670103399）
计算神经科学与类脑智能教育部重点实验室开放课题(25Z67010205) （25Z67010205）
