集成电路与嵌入式系统2025，Vol.25Issue(12)：40-51,12.DOI:10.20193/j.ices2097-4191.2025.0089
面向硬件缓存结构的数据布局优化研究综述
A survey of data layout optimization for cache hierarchy
ZHANG Yi 1ZHANG Yuling 1YANG Xuecong1
作者信息
- 1. College of Medicine and Biological Information Engineering,Northeastern University,Shenyang 110004,China
- 折叠
摘要
Abstract
Memory access latency remains a major bottleneck for many applications on modern processors.To optimize memory access performance,it is crucial to exploit the locality of reference in memory accesses.Data layout optimization techniques,through opera-tions such as merging,splitting,and reorganizing data structures,can significantly improve the locality of memory access.This paper first provides an overview of the technological background of memory architecture and data organization involved in layout optimization techniques.Then introduces the key issues that data orchestration techniques aim to address,the core ideas behind these techniques,and the main technologies upon which their implementation relies.Given the significant differences in storage and access patterns across vari-ous types of data,this paper focuses on systematically summarizing and categorizing relevant research,comparing the strengths and weaknesses of different approaches,and analyzing promising future research directions.关键词
缓存/程序局部性/数据布局/数据编排Key words
cache/program locality/data layout/data structure splicing分类
信息技术与安全科学引用本文复制引用
ZHANG Yi,ZHANG Yuling,YANG Xuecong..面向硬件缓存结构的数据布局优化研究综述[J].集成电路与嵌入式系统,2025,25(12):40-51,12.
