集成电路与嵌入式系统2025，Vol.25Issue(12)：52-58,7.DOI:10.20193/j.ices2097-4191.2025.0060
基于国产FPGA的PCIe接口DMA引擎设计
Design of PCIe DMA engine based on domestic FPGA
HE Lianjie 1CHEN Xiang 1WANG Xijun1
作者信息
- 1. School of Electronics and Information Technology,Sun Yat-sen University,Guangzhou 510006,China
- 折叠
摘要
Abstract
The PCIe interface bus enables low-latency,high-bandwidth data transmission between CPU and FPGA,with the key factor being the design of a DMA engine,allowing data transfer without CPU intervention.However,the majority of current CPU+FPGA data transmission solutions are based on foreign FPGA devices from Xilinx.There is a severe shortage of commercial IP cores for domestic FPGA,making it challenging to port these solutions to domestic FPGA platforms.To address this limitation,this paper designs a PCIe-based DMA engine and its corresponding driver on a domestic FPGA platform.The design encapsulates the parsing of transaction layer packets within the PCIe protocol stack,thereby reducing the development complexity of PCIe-based applications on domestic FPGA devices.The experimental results demonstrate that the DMA engine achieves a read throughput of 784 MB/s and a write throughput of 800 MB/s via PCIe 2.0 x2 bus,reaching 82％and 84％of the theoretical maximum bandwidth of PCIe 2.0 x2.关键词
FPGA/PCIe/DMA/驱动程序/数据传输系统Key words
FPGA/PCIe/DMA/driver/data transmission system分类
信息技术与安全科学引用本文复制引用
HE Lianjie,CHEN Xiang,WANG Xijun..基于国产FPGA的PCIe接口DMA引擎设计[J].集成电路与嵌入式系统,2025,25(12):52-58,7.
