电子学报2025，Vol.53Issue(8)：2719-2728,10.DOI:10.12263/DZXB.20250076
一种基于二分区四分支树的高效时钟树综合方法
An Efficient Clock Tree Synthesis Method Based on Bi-Partition Four-Branch Tree
摘要
Abstract
In very large scale integration(VLSI)design,efficient clock tree synthesis(CTS)is crucial for ensuring circuit performance and reliability.To address the co-optimization challenge of clock skew,latency,and power consump-tion in large-scale circuits,this paper proposes an efficient CTS method based on a bi-partition,four-branch H-like tree.In the bottom-up phase,the method first employs a greedy-based clustering(GBC)algorithm to enhance the fanout utilization of low-level buffers,significantly reducing the number of inserted buffers.Subsequently,it incorporates a buffer re-place-ment algorithm for the fine-grained control of local clock skew.During the top-down phase,it is first theoretically proven that uniformly inserting a specific number of buffers along a path minimizes clock latency,and a look-up table is construct-ed based on this principle to guide optimal buffer insertion.Next,the layout is vertically divided into two symmetrical half-regions from the clock source,and a four-branch H-like tree structure is constructed within each half-region.This structure not only applies the long-path buffer insertion algorithm to minimize global clock latency but also leverages its symmetry to merge buffers on symmetrical paths,further optimizing the buffer count while ensuring low clock skew and latency.Finally,to handle potential constraint violations during synthesis,the method first extracts insertable locations for buffers based on Boolean operations and then determines their optimal placement according to the properties of Manhattan rectangles.The proposed algorithm is validated on circuit instances with 1×105 to 2×105 flip-flops,and the results demonstrate its significant advantages.Compared to OpenROAD,our method reduces clock skew and power consumption by 32.3%and 29.9%,re-spectively.In comparison with GH-Tree,it achieves reductions of 59.9%in clock skew and 28.9%in power consumption,while maintaining a comparable global clock latency.关键词
二分区四分支树/缓冲器插入/时钟偏差/时钟延迟/时钟树综合Key words
bi-partition four-branch tree/buffer insertion/clock skew/clock latency/clock tree synthesis分类
信息技术与安全科学引用本文复制引用
郭静静,刘润衎,杨君威,王嘉伟,王冲,蔡志匡..一种基于二分区四分支树的高效时钟树综合方法[J].电子学报,2025,53(8):2719-2728,10.基金项目
江苏省自然科学基金(No.BK20240637) Natural Science Foundation of Jiangsu Province(No.BK20240637) （No.BK20240637）
