计算机应用与软件2025，Vol.42Issue(12)：51-57,70,8.DOI:10.3969/j.issn.1000-386x.2025.12.008
基于共享总线互连的多核堆栈处理器架构设计
MULTI-CORE STACK PROCESSOR ARCHITECTURE DESIGN BASED ON SHARED BUS INTERCONNECTION
摘要
Abstract
With the development of the embedded system,single-core stack processor cannot meet the requirements of practical application in development cost,execution speed and power consumption.In order to improve the performance of stack processor and explore the value of multi-core stack processor,this paper adopted WISHBONE shared bus interconnect architecture.Through designing multi-core stack processor architecture,Forth system instructions,bus arbitration,and Universal Asynchronous Receiver/Transmitter(UART),a multi-core stack processor based on shared bus interconnection was initially constructed.The structure of the new processor was described by Verilog and VHDL language,the function was simulated by ISim tool,and the functionality was implemented on the field programmable gate array(FPGA)chip ultimately.The experimental results show that the design uses effective bus arbitration to achieve high computing performance with low hardware cost and power consumption,which lays a good foundation for further research and application of multi-core stack processor architecture.关键词
Forth系统/堆栈处理器/多核处理器/总线仲裁Key words
Forth system/Stack processor/Multi-core processor/Bus arbitration分类
信息技术与安全科学引用本文复制引用
陈林,周永录,刘宏杰,代红兵..基于共享总线互连的多核堆栈处理器架构设计[J].计算机应用与软件,2025,42(12):51-57,70,8.基金项目
国家自然科学基金项目(61962060). （61962060）
