信息工程大学学报2025，Vol.26Issue(6)：668-673,6.DOI:10.3969/j.issn.1671-0673.2025.06.006
面向软件定义互连芯片的多协议SerDes时序约束方法
Multi-Protocol SerDes Timing Constraints Method for Software-Defined Interconnect Chips
摘要
Abstract
Multi-protocol SerDes is a key circuit module for software-defined interconnect chips.To meet the requirements of various protocol specifications and multiple rates for SerDes circuits in such chips,a multi-protocol SerDes timing constraints method for software-defined interconnect chips is de-signed and implemented.Firstly,the rate and clock requirements of SerDes for different protocols are clarified through analysis of the clock structure of multi-protocol SerDes.Secondly,internal and exter-nal clock constraints with protocol tags of SerDes are designed for the clock requirements of four proto-cols,and a single packetized constraint file is generated.Finally,timing verification and tape-out test-ing demonstrate that all timing paths meet the timing requirements,with the timing constraints design being confirmed as correct and complete.关键词
多协议SerDes/时序约束/静态时序分析/软件定义互连/时序收敛Key words
multi-protocol SerDes/timing constraints/static timing analysis/software-defined inter-connect/timing closure分类
信息技术与安全科学引用本文复制引用
ZHANG Li,DONG Chunlei,LI Peijie,ZHANG Xia,HU Yanbin..面向软件定义互连芯片的多协议SerDes时序约束方法[J].信息工程大学学报,2025,26(6):668-673,6.基金项目
国家重点研发计划(2022YFB2901000) （2022YFB2901000）
