真空电子技术Issue(6)：26-30,50,6.DOI:10.16540/j.cnki.cn11-2485/tn.2025.06.05
自带真空微腔垂直型真空晶体管仿真研究
Simulation Research on Vertical Vacuum Transistors with Built-in Vacuum Microcavities
摘要
Abstract
A micro/nano packaging method for vertical vacuum channel transistors is designed to solve the low vacuum problem in micro/nano packaging process.The fabrication of the transistor involves deposition and etching.The anode is formed during the process of inclined film deposition,concurrently with the formation of the vacuum chamber.The dimensions of the chamber opening and the thickness of the insulating layer directly impact the electrical performance of the device,and the large pressure difference between the inside and outside of the chamber affects the stability of its mechanical structure.The multi-physics simulation software COMSOL is utilized to simulate and analyze the mechanical properties of the vacuum chamber and the electrical characteristics of the device.The findings suggest that,under constant voltage conditions,thinner insulating layer exhibits greater cath-ode emission current,and a reduced diameter of the opening leads to enhanced gate control.The chamber with a volume of 1.4×10-19 m3 demonstrates adequate performance under the load of standard atmospheric pressure,indi-cating its pressure resistance meet the requirements for practical applications.The study provides a theoretical basis for the preparation of devices.关键词
场发射/真空沟道晶体管/真空封装Key words
Field emission/Vacuum channel transistor/Vacuum package分类
信息技术与安全科学引用本文复制引用
YAN Hao-yu,TANG Zhen-wu,ZHU Zhuo-ya,XIAO Mei,ZHANG Xiao-bing..自带真空微腔垂直型真空晶体管仿真研究[J].真空电子技术,2025,(6):26-30,50,6.基金项目
国家自然科学基金委重大研究计划培育项目(92264103) （92264103）
