舰船电子工程2025，Vol.45Issue(11)：144-147,4.DOI:10.3969/j.issn.1672-9730.2025.11.030
一种快捷的内存调试器设计
Design of a Fast Memory Debugger
张翔宇 1蔡文斋 2耿正 1王乾1
作者信息
- 1. 北京市遥感信息研究所 北京 100172
- 2. 中国电子科技集团公司第三十九研究所 西安 710054
- 折叠
摘要
Abstract
In order to build the debugging environment and solve the problem of sensing data which require for equipment de-bugging,a fast memory debugger based on Windows environment is designed.The memory debugger uses the special string grid technology to achieve the protocol data input,which can overload several grid functions to meet the memory editing,and then con-structs the memory debugging data that developers need to use.The memory debugger can modify the memory data by editing the da-ta,and then replace the change data of the business logic module.Dynamic array to store variable memory is used to achieve the pur-pose of debugging by programmers within the team.This memory debugger uses text and binary files to store variable data for other non-team programmers.At the same time,this paper uses broadcast message technology to design message filtering methods that other recipients need to overload,so that other processes can automatically perceive data changes.关键词
调试器/内存/数据格子/协议/函数/重载Key words
debugger/memory/grid/protoca/function/overload分类
信息技术与安全科学引用本文复制引用
张翔宇,蔡文斋,耿正,王乾..一种快捷的内存调试器设计[J].舰船电子工程,2025,45(11):144-147,4.
