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应用于CMOS图像传感器的12 bit全局共用型列级SAR ADC

郭仲杰 张金澳 许睿明 刘绥阳

电子科技大学学报2026,Vol.55Issue(1):77-84,8.
电子科技大学学报2026,Vol.55Issue(1):77-84,8.DOI:10.12178/1001-0548.2024271

应用于CMOS图像传感器的12 bit全局共用型列级SAR ADC

A 12 bit global shared column SAR ADC for CMOS image sensor

郭仲杰 1张金澳 1许睿明 1刘绥阳1

作者信息

  • 1. 西安理工大学自动化与信息工程学院,西安 710048
  • 折叠

摘要

Abstract

To address the issues of area and power consumption in traditional successive approximation register analog-to-digital converters(SAR ADCs)used in column-level readout circuits of CMOS image sensors,this paper proposes a high-speed SAR ADC with a globally shared DAC,tailored for large arrays.The proposed architecture is based on the concept of sharing a core DAC across multiple columns.It extracts the largest area-consuming component of traditional column-level SAR ADCs,the capacitor array DAC,and replaces it with a globally shared DAC that utilizes different weighted DAC signals,along with a multiplexer and adder,instead of traditional column-level multiplexing techniques.This method simplifies each column-level SAR ADC to only require a comparator,a multiplexer-adder,and partial digital logic,significantly reducing the area requirements while maintaining the speed and precision advantages of SAR ADCs. The proposed method was designed and simulated using a 55nm 1P4M CMOS process.With an analog voltage of 3.3V,a digital voltage of 1.2V,a clock frequency of 120MHz,and an input signal range of 1.6V,the 12-bit SAR ADC designed in this work achieves a static differential nonlinearity(DNL)of-0.8/0.8 LSB,an integral nonlinearity(INL)of-1.4/0.4 LSB,a signal-to-noise ratio(SNR)of 68.24 dB,and an effective number of bits(ENOB)of 11.02 bits.The total area is 10μm×350μm,with a power consumption of 264 μW.Compared to existing SAR ADCs,this design reduces the area requirements significantly while maintaining high speed and precision,providing theoretical support for the application of SAR ADCs in the column-level readout circuits of high-speed CMOS image sensors.

关键词

CMOS图像传感器/列级ADC/SAR ADC/全并行/全局共用

Key words

CMOS image sensor/column ADC/SAR ADC/fully parallel/global shared

分类

信息技术与安全科学

引用本文复制引用

郭仲杰,张金澳,许睿明,刘绥阳..应用于CMOS图像传感器的12 bit全局共用型列级SAR ADC[J].电子科技大学学报,2026,55(1):77-84,8.

基金项目

国家自然科学基金(62171367) (62171367)

陕西省创新能力支撑计划(2022TD-39) (2022TD-39)

西安理工大学校企协同基金(252062302) (252062302)

电子科技大学学报

1001-0548

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