电子科技大学学报2026，Vol.55Issue(1)：93-99,7.DOI:10.12178/1001-0548.2024291
基于特殊节点划分的低时延极化码SCL译码器架构
A low-latency architecture of SCL decoder for FPGA based on special node division
摘要
Abstract
Polar code proposed based on channel polarization is the only one that is proven to achieve the Shannon limit.The mainstream successive cancellation list(SCL)decoding algorithm shows the extremely high latency due to its massive path splitting and path metrics.To solve this problem,a low-latency SCL decoding hardware architecture based on special nodes is proposed in this paper.Pruning or split-reducing is considered for different nodes to reduce the decoding latency and improve the throughput with slight performance degradation.Moreover,to enhance the flexibility,the prior information of different code lengths and code rates is stored in the read-only memory(ROM)and is selected based on the input configuration.The implementation results of the proposed architecture on field programmable gate array(FPGA)show that the decoding cycles are reduced by 40.32%～56.87%compared with the standard SCL decoder with the code length varying from 128 to 1 024 bit and the code rate varying from 0.3 to 0.5.关键词
极化码/串行抵消列表/低时延/可配置译码器/可编程逻辑门阵列Key words
polar code/successive cancellation list/low latency/configurable decoder/FPGA分类
信息技术与安全科学引用本文复制引用
韩国军,曾子峰,董鹏,翟雄飞,史治平..基于特殊节点划分的低时延极化码SCL译码器架构[J].电子科技大学学报,2026,55(1):93-99,7.基金项目
国家自然科学基金(62301166,62471151,62371101) （62301166,62471151,62371101）
