集成电路与嵌入式系统2026，Vol.26Issue(2)：1-13,13.DOI:10.20193/j.ices2097-4191.2025.0105
VeriOptima:基于两阶多智能体的电路设计与优化AI框架
VeriOptima:a two-stage multi-agent AI framework for circuit design and optimization
摘要
Abstract
To address the challenges of functional correctness and optimization efficiency in automated hardware design using Large Lan-guage Models(LLMs),this paper presents VeriOptima,a two-stage framework that generates efficient gate-level netlists from natural language specifications.The first stage,ReasoningV,is a high-fidelity Verilog generation model that achieves 57.8%pass@1 accuracy on the VerilogEval-Human benchmark,rivaling state-of-the-art industry models.The second stage,CircuitMind,is a multi-agent opti-mization framework that refines the generated code to human-expert levels of efficiency.Evaluated on TC-Bench,a gate-level bench-mark derived from real design competitions,results show that using ReasoningV as a starting point and optimizing with CircuitMind leads to significantly better PPA metrics compared to other LLM-based flows.Ultimately,55.6%of the optimized implementations match or surpass the efficiency of top human experts.This work provides the first end-to-end solution that systematically overcomes both generation and optimization barriers,paving the way for fully automated,high-quality circuit design.Related code is open-sourced on GitHub.关键词
大型语言模型/电子设计自动化/Verilog生成/布尔优化/门级网表Key words
large language models/electronic design automation/Verilog generation/Boolean optimization/gate-level netlist分类
信息技术与安全科学引用本文复制引用
秦海岩,冯家豪,谢智威,李晶晶,康旺..VeriOptima:基于两阶多智能体的电路设计与优化AI框架[J].集成电路与嵌入式系统,2026,26(2):1-13,13.基金项目
北京市科技新星计划资助(20250484807) （20250484807）
