集成电路与嵌入式系统2026，Vol.26Issue(2)：53-62,10.DOI:10.20193/j.ices2097-4191.2025.0104
基于DCAP协同优化模型的USB2.0数据链路层设计
Design of USB 2.0 link layer based on the DCAP co-optimization model
吴宇涵 1王诗源 1陈小文 1邢世远1
作者信息
- 1. 国防科技大学 计算机学院,长沙 410073||国防科技大学 先进微处理器芯片与系统教育部重点实验室,长沙 410073
- 折叠
摘要
Abstract
Front-end RTL design is a critical phase determining a chip's performance,power,and area(PPA).Conventional methodolo-gies often prioritize functional implementation,lacking systematic optimization for PPA metrics.To address this,this paper proposes a multi-dimensional RTL optimization approach-the DCAP co-optimization model.This model establishes a framework encompassing four dimensions:Data-path(D),Computation(C),Area-management(A),and Power-management(P).Using the USB 2.0 data link layer as a case study,data throughput is enhanced via a coupled handshake scheme,computational efficiency is optimized using a real-time iterative CRC architecture,area overhead is controlled through resource management,and power consumption is reduced by impro-ving clock gating coverage.Back-end implementation results based on TSMC 65nm technology demonstrate that the design achieves a throughput of 52.3 MB/s(protocol efficiency:87%)in High-Speed mode,with a power consumption of 0.156 mW and an area of 3 333.6 μm2.Compared to the pre-optimized design,this represents a 39%reduction in power and a 23%reduction in area.In conclu-sion,the proposed DCAP model provides a reusable methodological guide for addressing PPA optimization challenges in digital circuit design at the RTL stage.关键词
DCAP模型/PPA优化/RTL设计/数据流优化/USB2.0Key words
DCAP model/PPA optimization/RTL design/data-path optimization/USB 2.0分类
信息技术与安全科学引用本文复制引用
吴宇涵,王诗源,陈小文,邢世远..基于DCAP协同优化模型的USB2.0数据链路层设计[J].集成电路与嵌入式系统,2026,26(2):53-62,10.
