集成电路与嵌入式系统2026，Vol.26Issue(2)：63-70,8.DOI:10.20193/j.ices2097-4191.2025.0098
基于Gm-TIA架构的100 Gb/s SerDes接收前端设计
Design of 100 Gb/s SerDes receiver front-end based on Gm-TIA
刘书涛 1邵磊1
作者信息
- 1. 中山大学 电子与信息工程学院(微电子学院),广州 510006
- 折叠
摘要
Abstract
This paper presents an analog front-end circuit for high-speed SerDes receivers,designed to address varying channel losses.Utilizing a transconductance-transimpedance(Gm-TIA)architecture,the circuit implements a continuous-time linear equalizer(CTLE)with a tunable peaking gain of 2.2～12.5 dB at the Nyquist frequency and a variable gain amplifier(VGA)with a gain range of-8～3.5 dB,offering flexibility for different channel characteristics.A complementary transconductance stage is employed to achieve current reuse,enhancing transconductance and power efficiency.A T-coil structure is designed to achieve broadband impedance matc-hing,considering parasitics from ESD,pads,and AC-coupling.Inductive peaking and tunable MOS resistors are adopted to extend bandwidth and enable continuous gain tuning.Fabricated in a 65 nm CMOS process,post-layout simulations show that the front-end achieves a peaking gain of 1.1～11.5 dB at 25 GHz Nyquist frequency,supports 100 Gb/s PAM4 signal transmission,and consumes 12.83 mW under a 1.2 V supply.关键词
高速串行器解串器/连续时间线性均衡器/可变增益放大器/Gm-TIA/CMOSKey words
SerDes/CTLE/VGA/Gm-TIA/CMOS分类
信息技术与安全科学引用本文复制引用
刘书涛,邵磊..基于Gm-TIA架构的100 Gb/s SerDes接收前端设计[J].集成电路与嵌入式系统,2026,26(2):63-70,8.
