集成电路与嵌入式系统2026，Vol.26Issue(3)：64-71,8.DOI:10.20193/j.ices2097-4191.2025.0103
100 Gb/s PAM-4有线接收机模拟前端设计研究
Research on analog front-end of 100 Gb/s PAM-4 wireline receiver design
马怡然 1张宸境 1高肈杉 1赵亚 1樊超1
作者信息
摘要
Abstract
To tackle the concurrent challenges of bandwidth,linearity,and integration in the analog front-end(AFE)of a 100 Gb/s PAM-4 wireline receiver for Chiplet interconnect applications,this paper presents a high-performance AFE architecture based on a trans-conductance-transimpedance amplifier(GM-TIA)continuous-time linear equalizer(CTLE).The proposed AFE efficiently compensates for channel loss while maintaining high linearity through an integrated broadband input matching network consisting of an asymmetric T-coil,a programmable attenuator,and an AC coupler.A two-stage cascaded GM-TIA-based CTLE enables wide-range gain tuning from low to high frequencies and also serves as a variable-gain amplifier(VGA).Designed in a 28-nm CMOS process,the AFE occupies a core area of 0.012 mm2 with the power dissipation of 9.94 mW.The equalization tuning range extends from 2.25 dB to 13.39 dB.After equalization,the 100 Gb/s PAM-4 output exhibits an eye height greater than 100 mV and an eye width exceeding 0.52 UI.关键词
芯粒互联/有线接收机/模拟前端/PAM-4/连续时间线性均衡器Key words
Chiplet/wireline receiver/analog front-end/PAM-4/continuous-time linear equalizer分类
信息技术与安全科学引用本文复制引用
马怡然,张宸境,高肈杉,赵亚,樊超..100 Gb/s PAM-4有线接收机模拟前端设计研究[J].集成电路与嵌入式系统,2026,26(3):64-71,8.
