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Optimizing 55 nm split-gate memory for compute-in-memory:a focus on floating-gate engineering

Wanyi Ling Xuan Li Dertsyr Fan Ichun Chuang Tzung Wen Cheng Chenming Tsai Dawei Gao Ranran Liu Kun Ren Dianyu Qi Yongyu Wu Guangji Li Miao Zhou Qingshuang Xu Zhenghui Xia

半导体学报（英文版）2026，Vol.47Issue(3)：46-53,8.

半导体学报（英文版）2026，Vol.47Issue(3)：46-53,8.DOI:10.1088/1674-4926/25060033

Optimizing 55 nm split-gate memory for compute-in-memory:a focus on floating-gate engineering

Wanyi Ling ¹Xuan Li ²Dertsyr Fan ³Ichun Chuang ³Tzung Wen Cheng ³Chenming Tsai ³Dawei Gao ⁴Ranran Liu ¹Kun Ren ¹Dianyu Qi ¹Yongyu Wu ²Guangji Li ²Miao Zhou ²Qingshuang Xu ²Zhenghui Xia²

作者信息

1. College of Integrated Circuits,Zhejiang University,Hangzhou 310000,China
2. Zhejiang ICsprout Semiconductor,Hangzhou 311200,China
3. IOTMemory Technology Inc.,Taipei City 10592,China
4. College of Integrated Circuits,Zhejiang University,Hangzhou 310000,China||Zhejiang ICsprout Semiconductor,Hangzhou 311200,China
折叠

摘要

关键词

split-gate/floating-gate/55 nm technology node/computation-in-memory

Key words

split-gate/floating-gate/55 nm technology node/computation-in-memory

引用本文复制引用

Wanyi Ling,Xuan Li,Dertsyr Fan,Ichun Chuang,Tzung Wen Cheng,Chenming Tsai,Dawei Gao,Ranran Liu,Kun Ren,Dianyu Qi,Yongyu Wu,Guangji Li,Miao Zhou,Qingshuang Xu,Zhenghui Xia..Optimizing 55 nm split-gate memory for compute-in-memory:a focus on floating-gate engineering[J].半导体学报（英文版）,2026,47(3):46-53,8.

基金项目

This paper was supported by National Key Research and Development Program of China(2022YFF0605803),Zhejiang key R&D project(2023C01017),and the Zhejiang Key Research and Development Project(2024SJCZX0030).Thanks Zhejiang Technology Innovation Center of CMOS IC Manufac-ture Process and Design for supporting us to do this research. （2022YFF0605803）

半导体学报（英文版）

ISSN：1674-4926

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