集成电路与嵌入式系统2026，Vol.26Issue(4)：26-33,8.DOI:10.20193/j.ices2097-4191.2025.0137
面向SoC内存的流水线奇偶校验电路设计与优化
Design and optimization of pipelined parity check circuit for SoC memory
摘要
Abstract
As SoC architectures evolve to meet the computational intensity of diverse AI applications,the pursuit of high-performance throughput must be balanced with uncompromising reliability.Consequently,parity check mechanisms have emerged as a cornerstone of modern circuit design,essential for safeguarding the integrity of massive data movement within the SoC fabric.However,in wide-bit-width data transmission scenarios,traditional parity check circuit designs face challenges such as high verification complexity and signifi-cant decoding latency,which in turn constrain the overall performance of SoCs,including system master clock frequency and data access bandwidth.To address this technical challenge,this paper innovatively proposes a multi-stage pipelined parity check circuit design method for the AXI bus in SoC memory.This design employs a pipelined architecture to optimize the verification process in stages,sig-nificantly reducing the critical path delay in the data pathway.The experiment results demonstrate that,at a minimal cost of a 0.47%increase in total circuit area and a 0.24%rise in power consumption,the proposed design method achieves timing optimization of the date read/write bus critical path,reducing the maximum delay of the AXI bus write and read data circuit paths by 18.62%and by 25.60%respectively,effectively enhancing the overall performance and reliability of the SoC.关键词
多级流水线/时序优化/奇偶校验/集成电路/片上系统/双倍数据速率同步动态随机存储器Key words
multi-level pipeline/timing optimization/parity check/integrated circuit/SoC/DDR SDRAM分类
信息技术与安全科学引用本文复制引用
马敬博,张光达,王会权,裴秉玺,方健,黄成龙,罗慧,蒋艳德..面向SoC内存的流水线奇偶校验电路设计与优化[J].集成电路与嵌入式系统,2026,26(4):26-33,8.基金项目
中国国家自然科学基金(62372461) （62372461）
智强基金 （）
