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基于FPGA的万兆以太网在雷达数字前端设计中的实现

唐浩

集成电路与嵌入式系统2026,Vol.26Issue(4):76-83,8.
集成电路与嵌入式系统2026,Vol.26Issue(4):76-83,8.DOI:10.20193/j.ices2097-4191.2025.0143

基于FPGA的万兆以太网在雷达数字前端设计中的实现

Implementation of 10-Gigabit ethernet based on FPGA in radar digital front-end design

唐浩1

作者信息

  • 1. 成都天奥信息科技有限公司,成都 610041
  • 折叠

摘要

Abstract

This paper presents the design of a high-speed real-time signal processing radar digital front-end based on Xilinx FPGA.The FPGA in this radar front-end fully utilizes its abundant resources,including logic,RAM,DSP,and high-speed interfaces,to implement functional modules such as 10-Gigabit Ethernet,Microblaze,and high-speed cache.This enables the FPGA to perform control,prepro-cessing,and high-speed data transmission,resulting in a radar processing front-end with a simple hardware structure,high signal pro-cessing capability,and fast data transmission speed.To meet the data transmission capacity requirements,in the software implementa-tion,the high-speed data read-write timing is meticulously designed according to radar waveform characteristics.This design has been successfully applied in real-time processing for surveillance radar projects,achieving excellent results.

关键词

FPGA/雷达/MTU/UDP/万兆以太网/Microblaze/SFDR

Key words

FPGA/Radar/MTU/UDP/10-Gigabit Ethernet/Microblaze/SFDR

分类

信息技术与安全科学

引用本文复制引用

唐浩..基于FPGA的万兆以太网在雷达数字前端设计中的实现[J].集成电路与嵌入式系统,2026,26(4):76-83,8.

集成电路与嵌入式系统

1009-623X

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