舰船电子工程2026，Vol.46Issue(1)：139-146,8.DOI:10.3969/j.issn.1672-9730.2026.01.028
时钟稳定性研究
Research on Clock Stability
朱振麟 1焦新泉1
作者信息
- 1. 中北大学仪器科学与动态测试教育部重点实验室 太原 030051||中北大学电子测试技术国家重点实验室 太原 030051
- 折叠
摘要
Abstract
The 125 MHz clock jitter generated by the FPGA loopback will be aggravated after being kept in the low tempera-ture environment of-40℃for 1 hour,which affects the establishment of the link of the recording equipment and the accuracy of data acquisition and storage,and brings serious impact on the reliability of the system.To address this problem,the solution of adding CDCM61004 clock chip instead of MMCM to generate high-speed clock on the hardware of the acquisition device is proposed.Tak-ing into account the demand for miniaturization of storage devices,on the premise of not increasing the size and cost of the device,the use of software means to reduce clock jitter by upgrading the 3-stage PLL filtering on the basis of DCM.After several experi-ments in-40℃low temperature environment,the optimized and upgraded recording device has no unsuccessful link establishment and data error code phenomenon,which confirms the feasibility of the solution.关键词
抖动/FPGA/低温/PLLKey words
jitter/FPGA/low temperature/PLL分类
信息技术与安全科学引用本文复制引用
朱振麟,焦新泉..时钟稳定性研究[J].舰船电子工程,2026,46(1):139-146,8.
