半导体学报（英文版）2026，Vol.47Issue(4)：65-76,12.DOI:10.1088/1674-4926/25060030
Effects of cell topology and JFET width on depletion layer of SiC MOSFET
Effects of cell topology and JFET width on depletion layer of SiC MOSFET
Bofeng Zheng 1Houcai Luo 1Huan Wu 1Jingping Zhang 1Xianping Chen2
作者信息
- 1. Key Laboratory of Optoelectronic Technology&Systems,Chongqing University,Chongqing 400044,China
- 2. Key Laboratory of Optoelectronic Technology&Systems,Chongqing University,Chongqing 400044,China||Key Laboratory of Power Transmission Equipment&System Security and New Technology,Chongqing University,Chongqing 400044,China
- 折叠
摘要
关键词
4H-SiC/depletion layer/gate oxide capacitance/JFET region/reliabilityKey words
4H-SiC/depletion layer/gate oxide capacitance/JFET region/reliability引用本文复制引用
Bofeng Zheng,Houcai Luo,Huan Wu,Jingping Zhang,Xianping Chen..Effects of cell topology and JFET width on depletion layer of SiC MOSFET[J].半导体学报（英文版）,2026,47(4):65-76,12.
