摘要
Abstract
This paper presents a programmable computing-in-memory circuit based on a 4T GC-eDRAM cell,designed for cryogenic ap-plications.First,a dual word-line readout structure is proposed to prevent data corruption in the memory cell.Second,leveraging the characteristic that computational data tends to be zero-biased,a zero-enhanced decoder/encoder circuit is proposed to further reduce read power consumption.Finally,a programmable near-memory computing circuit is implemented,capable of supporting both logic opera-tions and arithmetic operations such as addition,subtraction,multiplication,and division.The design was fabricated and verified using a TSMC 65nm low power process.Experimental results demonstrate that the proposed circuit achieves a maximum speedup of 6×for convolution operations and 12.3×for lightweight data encryption.Within the temperature range of-40℃to 85℃,the circuit exhib-its superior read,write and computing energy efficiency compared to a 6T SRAM structure.It is worth noting that,as this circuit is based on a GC-eDRAM design,its performance is closely linked to leakage current and refresh frequency.As the temperature is low-ered further into the liquid nitrogen range(77 K),the leakage current of MOS transistors is drastically reduced,enabling the refresh cycle to be significantly extended.This maximizes the circuit's energy efficiency ratio,endowing the designed circuit substantial advanta-ges in low-temperature computing applications.关键词
GC-eDRAM/低温存算/双字线/强零编解码电路/存算一体电路Key words
GC-eDRAM/low-temperature computing-in-memory/dual word-line/zero-enhancement decoder/encoder/computing-in-memory circuit分类
信息技术与安全科学
