集成电路与嵌入式系统2026，Vol.26Issue(5)：46-56,11.DOI:10.20193/j.ices2097-4191.2025.0123
基于FPGA的新型自校准高分辨率DPWM设计
Design of a new self-calibrated high-resolution DPWM based on FPGA
摘要
Abstract
DPWM is the core of digital control switching power supply.To address the conflict between the high resolution of DPWM and the system operating frequency,this paper designs a high-resolution DPWM scheme based on FPGA.A 4 ns 14 bit low-resolution delay unit is implemented based on the traditional counter-comparator structure,and a 100 ps 7 bit high-resolution delay unit is achieved using a carry delay chain.The novel hybrid structure proposed in this paper can independently adjust the high-resolution delay of the rising and falling edges and has a real-time self-calibration unit to ensure the adjustment accuracy of the delay line and prevent the gradient adjust-ment from crossing the low-resolution period and causing offset stability issues.This architecture uses a cascaded carry delay chain de-sign and global PWM drive via a BUFG,enabling automatic global routing and improving system portability.The experiment results demonstrate that the high-resolution delay units of this architecture are all below 100 ps,with an average delay of 67 ps,and it has high linearity and monotonicity.关键词
DPWM/高分辨率/FPGA/延迟线/校准Key words
DPWM/high-resolution/FPGA/delay line/calibration分类
信息技术与安全科学引用本文复制引用
杨园格,翟书颖,保慧琴,李茹..基于FPGA的新型自校准高分辨率DPWM设计[J].集成电路与嵌入式系统,2026,26(5):46-56,11.基金项目
西安明德理工学院科研基金项目(2023MDY02) （2023MDY02）
陕西省教育厅创新训练项目(S202513894066) （S202513894066）
