集成电路与嵌入式系统2026，Vol.26Issue(5)：65-74,10.DOI:10.20193/j.ices2097-4191.2025.0092
基于GCN-MLP混合模型的延迟优化敏感单元预测方法
A GCN-MLP hybrid model for delay-optimization-sensitive cell prediction
成泽祥 1冯超超 2赵振宇 2罗元盛1
作者信息
- 1. 长沙理工大学 计算机学院,长沙 410015
- 2. 国防科技大学 计算机学院,长沙 410073||国防科技大学 先进微处理器芯片与系统重点实验室,长沙 410073
- 折叠
摘要
Abstract
With the continuous scaling down of transistor technology nodes,achieving timing closure in nanoscale integrated circuits faces severe challenges.Although traditional circuit simulation can evaluate the performance of cell netlists and layouts,its computationally intensive nature results in prohibitively high time costs.This paper proposes a delay-optimization-sensitive cell prediction model that in-tegrates Graph Convolutional Networks(GCN)and Multilayer Perceptrons(MLP).The approach first dynamically adjusts transistor sizes in the netlist based on input signal states,then employs GCN to parse cell netlist structures and generate homogeneous graph rep-resentations of transistor connectivity relationships and process parameters.Finally,these topological features are fused with conven-tional timing characteristics and fed into an MLP to predict cell optimization potential,thereby identifying delay-optimization-sensitive cells.The experimental results demonstrate prediction accuracy rates of 83.2%for the top 10 delay-optimization-sensitive cells with the highest optimization potential and 75.3%for the top 5 such cells.Compared to SPICE simulation,the time required to identify delay-optimization-sensitive cells is reduced from hours to minutes,achieving approximately 600 times acceleration.This method can accurately identify critical optimization targets,provide layout designers with transistor-level optimization parameters,and significantly improve timing closure efficiency.关键词
机器学习/延迟优化敏感单元/晶体管级时序优化/电路仿真/电路拓扑Key words
machine learning/delay-optimization-sensitive cell/transistor-level timing optimization/circuit simulation/circuit topology分类
信息技术与安全科学引用本文复制引用
成泽祥,冯超超,赵振宇,罗元盛..基于GCN-MLP混合模型的延迟优化敏感单元预测方法[J].集成电路与嵌入式系统,2026,26(5):65-74,10.
