光通信技术2026，Vol.50Issue(2)：103-108,6.DOI:10.13921/j.cnki.issn1002-5561.2026.02.017
面向调制格式识别的稀疏CNN FPGA加速器设计
Design of sparse CNN FPGA accelerator for modulation format recognition
摘要
Abstract
To achieve efficient modulation format recognition in embedded scenarios with limited logic and power resources,a sparse convolutional neural network(CNN)field-programmable gate array(FPGA)accelerator designed for modulation for-mat recognition is presented.First,the baseline CNN model undergoes unstructured pruning,8-bit dynamic fixed-point quanti-zation,and layer fusion,significantly compressing the model size.Subsequently,a hardware acceleration architecture based on the ABM-SpConv algorithm is designed,employing weight re-encoding and a single-write multi-read cache structure to opti-mize parallel convolution and data access efficiency.Experimental results show that on the XC7A200 FPGA platform,the de-sign achieves an average recognition accuracy of 90.2%with an on-chip power consumption of 1.455 W,a per-frame process-ing time of 142.48 μs,and an energy efficiency ratio of 0.232 GOP/(s·W-1),outperforming central processing unit(CPU)and graphics processing unit(GPU)platforms for the same task.This provides a feasible path for deploying modulation format rec-ognition in resource-constrained environments.关键词
卷积神经网络/加速器/现场可编程门阵列/调制格式识别Key words
convolutional neural network/accelerator/field-programmable gate array/modulation format recognition分类
信息技术与安全科学引用本文复制引用
孔一卜,黎海文,曾庆辉,陆叶..面向调制格式识别的稀疏CNN FPGA加速器设计[J].光通信技术,2026,50(2):103-108,6.基金项目
中央引导地方科技发展资金项目(桂科ZY24212030)资助. （桂科ZY24212030）
