舰船电子工程2026，Vol.46Issue(2)：161-166,6.DOI:10.3969/j.issn.1672-9730.2026.02.032
亿门级FPGA互连线资源测试方法研究
Research on Testing Methods for Interconnection Line Resources of Billion Gate FPGA
摘要
Abstract
In order to solve the problem that the interconnection line resources of billion-gate level FPGA cannot be tested,this article proposes a global interconnection line routing method based on the TCL command line and the internal resource structure of billion-level FPGA.The interconnection line resource test design problem cannot be implemented in the development environ-ment Vivado,and the look-up table is used as a relay unit to compensate for the driving capability and extended routing direction,and ATE is used to complete test verification and automated testing.This method has good convenience and controllability whether it is used for automated mass production test vector design or interconnect line fault diagnosis.关键词
亿门级FPGA/互连线/TCL/查找表/ATE/测试验证Key words
billion gate FPGA/interconnection line/TCL/LUT/ATE/test verification分类
信息技术与安全科学引用本文复制引用
林晓会,宋国栋,陈宇轩,解维坤..亿门级FPGA互连线资源测试方法研究[J].舰船电子工程,2026,46(2):161-166,6.基金项目
十四五装备预研项目(编号:31517040401)资助. （编号:31517040401）
