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基于FPGA的信号发生器设计与实现

程春雨 谭锦 贺鑫 吴振宇 谢艾林

实验科学与技术2026,Vol.24Issue(3):68-75,8.
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实验科学与技术2026,Vol.24Issue(3):68-75,8.DOI:10.12179/1672-4550.20240553

基于FPGA的信号发生器设计与实现

Design and Implementation of a Signal Generator Based on FPGA

程春雨 1谭锦 1贺鑫 2吴振宇 3谢艾林4

作者信息

  • 1. 大连理工大学 控制科学与工程学院,大连 116024
  • 2. 清华大学 网络科学与网络空间研究院,北京 100084
  • 3. 大连理工大学 创新创业学院,大连 116024
  • 4. 东北大学 信息科学与工程学院,沈阳 110819
  • 折叠

摘要

Abstract

Direct digital synthesis(DDS)technology offers advantages such as high frequency resolution,fast switching speed,and continuous phase.Consequently,it is widely applied in fields such as wireless communication,satellite navigation,and electronic reconnaissance.Using DDS technology,along with development tools ModelSim SE and Quartus Ⅱ 13.0 and the hardware description language Verilog HDL,this study completed the design,simulation,and online logic debugging and analysis of the signal generator.The system is capable of:outputting sine,triangular,and square waves;adjusting signal frequency,amplitude,and duty cycle via buttons;and observing the output signal using an oscilloscope.Simulation and practical verification show that the output frequency ranges from 1 Hz to 1 MHz,the output peak-to-peak amplitude is continuously adjustable within 0~6.4 V,and the duty cycle is continuously adjustable from 0%to 100%.The implementation of the system provides a referable teaching case for students to learn Field Programmable Gate Array(FPGA)courses.

关键词

FPGA/信号发生器/Verilog HDL/实验教学案例

Key words

FPGA/signal generator/Verilog HDL/experimental teaching case

分类

社会科学

引用本文复制引用

程春雨,谭锦,贺鑫,吴振宇,谢艾林..基于FPGA的信号发生器设计与实现[J].实验科学与技术,2026,24(3):68-75,8.

基金项目

教育部基本科研业务项目(DUT24BK004) (DUT24BK004)

教育部本科教学质量工程项目(ZL2023040,ZL2022118,ZL2021235). (ZL2023040,ZL2022118,ZL2021235)

实验科学与技术

1672-4550

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