摘要
Abstract
The post-quantum cryptographic algorithm ML-KEM has emerged as a key standard for resisting quantum computing attacks,and its high-speed hardware implementation is crucial for future network security.This paper proposes a hardware architecture for ML-KEM and optimizes several specific modules within the design.For the encoding and decoding operations,FIFO-based processing is employed to reduce resource consumption.In addition,the compression operation is analyzed to eliminate division operations during the compression process,and division and rounding are combined through specific parameter selection.Furthermore,a compact operation schedule is adopted to increase parallelism while reducing the overall computation latency.The proposed design is implemented and synthesized on a Xilinx Artix-7 platform.Experimental results show that the maximum operating frequency reaches 125 MHz,with resource utilization of 19791 LUTs,8 364 FFs,22 BRAMs,and 9 DSPs.Under three security levels,the latencies of key generation,encapsulation,and decapsulation are 3 541/4 957/6 593 cycles,4 042/5 504/7 183 cycles,and 6 822/9 072/11274 cycles,respectively.The proposed architecture achieves a favorable balance between resource overhead and computational performance.关键词
后量子密码/ML-KEM/Kyber/硬件加速/多项式运算Key words
post-quantum cryptography/ML-KEM/Kyber/hardware acceleration/polynomial arithmetic分类
信息技术与安全科学
