集成电路与嵌入式系统2026，Vol.26Issue(6)：10-18,9.DOI:10.20193/j.ices2097-4191.2025.0150
基于FPGA的ESC芯片冗余通信接口设计
Design of redundant communication interface for ESC chip based on FPGA
李响 1刘晖 2董为轩 1成元庆1
作者信息
- 1. 北京航空航天大学 集成电路科学与工程学院,北京 100191
- 2. 北京航空航天大学 集成电路科学与工程学院,北京 100191||中电智能科技有限公司,北京 102200
- 折叠
摘要
Abstract
To achieve independent controllability and enhance the communication reliability of the EtherCAT Slave Controller(ESC),this paper proposes an FPGA-based redundant communication interface.The design adopts a modular architecture with the innovative integration of hardware modules,including link redundancy processing,multi-path frame forwarding,EtherCAT frame parsing,and configurable timing compensation.It supports dual-link redundancy backup and enables real-time detection and isolation of erroneous frames.The system performs automatic frame forwarding and achieves microsecond-level latency through parallel hardware processing.FPGA test results demonstrate that the interface maintains stable communication during single-link failures while consuming minimal hardware resources.The proposed solution effectively improves the fault tolerance and real-time performance of ESC communications,laying a solid technical foundation for the independent development of high-reliability industrial communication chips.关键词
EtherCAT/ESC芯片/FPGA/MII接口/工业以太网/冗余通信Key words
EtherCAT/ESC chip/FPGA/MII interface/industrial Ethernet/redundant communication分类
信息技术与安全科学引用本文复制引用
李响,刘晖,董为轩,成元庆..基于FPGA的ESC芯片冗余通信接口设计[J].集成电路与嵌入式系统,2026,26(6):10-18,9.
