集成电路与嵌入式系统2026，Vol.26Issue(6)：19-24,6.DOI:10.20193/j.ices2097-4191.2025.0128
基于逻辑分析仪的CPLD配置向量生成方法
A logic analyzer-based approach to generation of CPLD configuration vectors
摘要
Abstract
The stringent application scenarios of CPLD devices demand high-reliability testing with rigorous standards.To address issues such as the complexity and low efficiency of testing CPLD devices via host computers,a method for generating CPLD configuration vec-tors based on a logic analyzer is proposed.Using a domestic CPLD as an example,this method employs a logic analyzer to capture the JTAG download configuration data in real time.Through protocol decoding and in-depth analysis of the decoded configuration data,con-figuration vectors are generated based on the SVF standard statement format.The configuration vectors conversion and online configura-tion testing verification using ATE were completed.The test results effectively demonstrate the correctness of the generated configura-tion vectors and the feasibility of the proposed method,providing significant guidance for the subsequent use of ATE in automated mass production testing of CPLD devices.关键词
CPLD/逻辑分析仪/ATE/SVF/配置向量/测试验证Key words
CPLD/logic analyzer/ATE/SVF/configuration vector/test verification分类
信息技术与安全科学引用本文复制引用
林晓会,陶开强,宋国栋,陈龙,解维坤..基于逻辑分析仪的CPLD配置向量生成方法[J].集成电路与嵌入式系统,2026,26(6):19-24,6.基金项目
国家自然科学基金项目(92573109) （92573109）
