电子器件2026，Vol.49Issue(2)：254-259,6.DOI:10.3969/j.issn.1005-9490.2026.02.003
一种针对Crook位压缩算法的硬件结构设计与实现
A Hardware Structure Design and Implementation for the Crook Bit Compression Algorithm
贺泽斌 1陈本源 1徐鹏 1李根1
作者信息
- 1. 湖北工业大学理学院,湖北 武汉 430068
- 折叠
摘要
Abstract
In order to meet the high compression ratio requirements for applications such as network transmission,the hardware implemen-tation of the Crook bit compression algorithm is developed.Firstly,in accordance with the characteristics of the Crook algorithm,a hard-ware structure is designed,including modules for'model updating'and'encoding and decoding'.To enhance the portability of this hard-ware structure,APB and AXI bus interfaces are introduced,facilitating tight integration with other SOC architectures.The validation of this hardware structure is carried out on Xilinx FPGA chips,and experimental data indicate that,under the conditions of using 1 433 slice LUTs and 1 099 slice registers,this hardware structure ensures the reliability of data compression while maintaining the compression ratio of the Crook algorithm intact.关键词
硬件加速/Crook算法/压缩算法/FPGAKey words
hardware acceleration/Crook algorithm/compression algorithm/FPGA分类
信息技术与安全科学引用本文复制引用
贺泽斌,陈本源,徐鹏,李根..一种针对Crook位压缩算法的硬件结构设计与实现[J].电子器件,2026,49(2):254-259,6.
