重庆工商大学学报（自然科学版）2026，Vol.43Issue(3)：45-52,8.DOI:10.16055/j.issn.1672-058X.2026.0003.006
基于FPGA的YOLOv4-tiny网络的硬件加速与实现
Hardware Acceleration and Implementation of YOLOv4-Tiny Network Based on FPGA
摘要
Abstract
Objective To enhance the computational performance and energy efficiency ratio of object detection algorithms on edge hardware platforms under resource-constrained conditions,this paper proposes and verifies an edge hardware platform based on field programmable gate array(FPGA)for accelerating the YOLOv4-tiny network.Methods High-level synthesis(HLS)was used to design and optimize the operators and modules of the algorithm in a highly parallel manner.To improve design throughput,a double-buffering strategy was adopted to increase system resource utilization.Additionally,techniques such as fusion of convolutional and batch normalization(BN)layers and model quantization were applied to reduce model parameters and enhance computational density.Results Experiments conducted on the PYNQ-Z2 platform demonstrate that the accelerator achieved a computational performance of 15.33 GOPS with a total power consumption of 2.65 W.Compared to existing FPGA platforms,the proposed design improved computational performance by 2.79 times,while achieving a 29.5-fold increase in energy efficiency ratio compared to CPU platforms.Conclusion The proposed method effectively enhances the acceleration of the YOLOv4-tiny network on edge FPGA platforms,providing a valuable reference for the acceleration research of object detection algorithms on hardware platforms.关键词
现场可编程门阵列/高层次综合/YOLO/硬件加速Key words
field programmable gate array/high-level synthesis/YOLO/hardware acceleration分类
信息技术与安全科学引用本文复制引用
李雷,黎远松,石睿..基于FPGA的YOLOv4-tiny网络的硬件加速与实现[J].重庆工商大学学报（自然科学版）,2026,43(3):45-52,8.基金项目
国家自然科学基金项目资助(42074218). （42074218）
