电气技术2026，Vol.27Issue(6)：49-53,5.
基于现场可编程门阵列的硬件加速系统教学实验设计
Design of teaching experiment for hardware acceleration system based on field programmable gate array
摘要
Abstract
Electronic design automation(EDA)technology course is a professional,applied and practical course for electronic communication majors in universities.Field programmable gate array(FPGA)with programmability and flexibility,as the hardware carrier of the course,can be applied to realizing complex systems and complex algorithms,and has excellent performance in various fields such as artificial intelligence,communication and medicine.To address the lack of systematic and hardware-software co-design in existing EDA course experiments,the research of the experiment teaching combining FPGA and artificial intelligence algorithms is carried out,and the design ability of the system-level and software-hardware coordination is cultivated by designing the FPGA-based neural network hardware acceleration system,which has certain reference significance for the FPGA experiment and the FPGA course design of the electronic information majors.关键词
电子设计自动化(EDA)技术/现场可编程门阵列(FPGA)/系统级/软硬件协调Key words
electronic design automation(EDA)technology/field programmable gate array(FPGA)/system level/software-hardware coordination引用本文复制引用
高家宝,苏婷..基于现场可编程门阵列的硬件加速系统教学实验设计[J].电气技术,2026,27(6):49-53,5.基金项目
海南省高等学校教育教学改革研究项目(Hnjg2025ZD-9)海南大学教育教学改革研究项目(hdjy2366) （Hnjg2025ZD-9）
